Articles from Chiplet Summit

Chiplet Summit announces its fourth annual conference on February 17-19, 2026, at the Santa Clara Convention Center. The 2026 event will highlight the next wave of innovation in chiplet-based design and integration, focusing on advanced packaging, die-to-die interfaces, and AI acceleration. Attendees will explore how chiplets enable faster design cycles, higher yields, and more powerful systems at lower cost. The event also covers high-bandwidth memory, a low-cost way to create a supercomputer-in-a-package that can support generative AI.

Emphasis is on AI applications. The third annual Chiplet Summit, to occur on January 21-23 at the Santa Clara Convention Center, has now set its final keynote schedule.

Chiplet Summit’s 2025 event offers the last word on leading-edge chip design at the Santa Clara Convention Center on January 21-23. The Tuesday tutorials cover advanced packaging technologies, die-to-die interfaces, design methods, working with foundries, and the Open Chiplet Economy. Wednesday sessions cover creating foundry-ready designs, getting the most from high-bandwidth memory (HBM), and system-technology co-optimization (STCO). Thursday panels discuss viable markets, making money with chiplets, and long-term trends.

Emphasis is on bringing diverse practitioners up to date on all aspects of chiplets. The third annual Chiplet Summit, to occur on January 21-23 at the Santa Clara Convention Center, has now set its pre-conference day schedule for Tuesday, January 21.

Chiplet Summit opens pre-registration today for its third annual event on January 21-23 at the Santa Clara Convention Center. All major chip makers have adopted chiplets as their way to produce devices at leading-edge nodes.

Chiplet Summit is the key show for a technology that AMD, Intel, and Samsung all use in creating their new chips. The 2025 event will be at the Santa Clara Convention Center on January 21-23. It covers design methods, interfaces, and packaging. It offers keynotes, tutorials, and sessions on recent advances, new tools, and likely breakthroughs. The emphasis is on showing specialists how to work together to reduce cost and time-to-market.

Chiplet Summit announces its third annual event on January 21-23 at the Santa Clara Convention Center. The 2025 meeting focuses on a new level in chip design: system-in-package (SiP). SiPs use advanced packaging to raise performance and reduce time-to-market. Co-optimization methods allow all design stages to proceed together. The event also covers supercomputer-in-a-package, a low-cost way to support generative AI.

Chiplet Summit announces Yole Group is returning as its market research partner for its second annual event. The Summit is on February 6-8 at the Santa Clara Convention Center. Yole Group will analyze the chiplet market and cover both short and long-term trends.

Chiplet Summit opens pre-registration today for its second annual event on February 6-8 at the Santa Clara Convention Center. Hundreds of registrants and many key exhibitors will be at the premier showcase for chiplet technology. All major chip makers have adopted chiplets as their approach to producing devices at leading-edge nodes.

The second annual Chiplet Summit, to occur on February 6-8 at the Santa Clara Convention Center, has now set its initial keynote schedule. Speakers will be:

Generative AI is today’s biggest technology news, and Chiplet Summit is therefore making it the focus of the 2024 event at the Santa Clara Convention Center on February 6-8. The Tuesday superpanel features leading experts expressing their views on “How Can Chiplets Accelerate Generative AI?”. The Wednesday plenary has Palo Alto Electron CEO Jawad Nasrullah presenting “Developing Chips for Tomorrow: You, Me, and ChatGPT®”. A Thursday session offers an annual update on generative AI applications.

Chiplet Summit announces that international consultant Mark Berry will be its packaging and test expert for the event on February 6-8, 2024 at the Santa Clara Convention Center. Mark will connect with new exhibitors, find exciting speakers, and emphasize the increasing importance of packaging and test in chip design.

Chiplet Summit announces its second annual event on February 6-8 at the Santa Clara Convention Center. This year’s conference focuses on techniques that extend Moore’s Law to ever-smaller dimensions. Chiplets reduce costs, increase modularity and scalability, and avoid wastage. They lead to more powerful chips and faster time-to-market. This year’s emphasis will be on co-design methods in which all stages of design proceed simultaneously. It will also focus on the fast-emerging area of generative AI with its huge demands.

Chiplet Summit debuted at the Doubletree by Hilton San Jose Hotel on January 24-26, 2023. It focused on using chiplets to make big chips easier and cheaper to design. 520 people registered for the first event to deal exclusively with all aspects of this promising new approach. Keynoters were Applied Materials, proteanTecs, Silicon Catalyst (discussing the US CHIPS Act), Intel, Corigine, and Open Compute Project. The conference also featured pre-conference tutorials on chiplets and the open chiplet economy, and panels on design challenges, breakthroughs, packaging, optimization, viable chiplet markets, and near-term trends. A superpanel moderated by international expert Jan Vardaman focused on successful co-package design. Leading exhibitors and sponsors were Applied Materials, Corigine, Open Compute Project, proteanTecs, Achronix, Adeia, Alphawave Semi, and Ventana Micro Systems. Slides from the sessions and keynotes will be available shortly on the website at no charge.

Chiplet Summit Covers the Latest Approaches. The new Chiplet Summit will help designers develop new chips faster and cheaper. The idea of dividing large chips into small units is a powerful approach that allows for drop-in design. However, it also introduces the new stage of heterogeneous integration in which everything must be put back together. The right package must be defined, the various chiplets must be fitted into it correctly, and a new high-speed die-to-die interface must interconnect them. Chiplet Summit will have pre-conference tutorials on packaging, interfaces, and test and integration. Keynotes and sessions will discuss the use of AI, co-optimization, co-package design, FPGA controllers, signal integrity issues, the use of IP, and successful implementations. Chiplets can do a lot, but integrating them can be time-consuming and expensive without the right tools. Chiplet Summit will review what’s available and how to obtain it. It will also have panels on choosing the right methods and optimizing applications, and vendors will show their approaches in the exhibit area.

Chiplet Summit, to be held January 24-26 at the Doubletree by Hilton San Jose Hotel, features 6 keynotes that will bring attendees up-to-date on what leading players are planning. Major company keynoters are Intel and Applied Materials. In addition, startups Corigine and proteanTecs, and the standards-developing Open Compute Project (OCP) will share their latest plans, and Silicon Catalyst will analyze the new $50 billion US Chips program.

Chiplet Summit, to be held January 24-26 at the DoubleTree by Hilton San Jose Hotel, will help designers go-to-market faster by using the latest design architecture – chiplets. All the leading semiconductor companies are now using them to speed up design at leading-edge process nodes. The Summit will help designers with the new stage of heterogeneous integration and the new requirement of implementing a die-to-die interface. It will also help them divide up designs properly, add design-for-test and design-for-manufacturing features, and implement both chiplet-level and package-level debug and test. Furthermore, it will offer insight into chiplet markets, packaging, and data management.

Chiplet Summit announces Yole Group as its market research partner for its first annual event. The Summit will occur on January 24-26 at the Doubletree San Jose. Yole Group will analyze the chiplet market and cover both short and long-term trends.

Chiplet Summit opens pre-registration today for its first annual event. It will occur on January 24-26 at the Doubletree by Hilton San Jose. Hundreds of registrants and many key exhibitors will be at the first showcase for chiplet technology, the latest approach for developing state-of-the-art chips. All leading chip makers have adopted chiplets as their approach to making devices at process nodes of 5 nm and below.

The first annual Chiplet Summit, to occur on January 24-26, 2023 at the DoubleTree by Hilton San Jose, has now set its initial keynote schedule. Speakers will be:

Chiplet Summit debuts at the San Jose Doubletree Hotel on January 24-26, 2023. It focuses on techniques that extend Moore’s Law to ever-smaller dimensions. Chiplets reduce costs, increase modularity and scalability, and avoid wastage and manufacturing defects. Chiplets lead to better chips and faster time-to-market.